ECE480/580 VHDL Code Evaluation Rubric (Applicable to all assignments)

VHDL Evaluation (Grading) Rubric

Laboratory and Project Report Evaluation (Grading) Rubric

Digital Systems Design -- Homework Assignments

Assignment Assigned Date Due Date
Homework #1 September 8, 2016 September 15, 2016

Digital Systems Design -- Lab Assignments

IEEE Information for Authors

Preparation of Papers for IEEE TRANSACTIONS and JOURNALS

Assignment Assigned Date Due Date
Lab #1 August 25, 2016 September 8, 2016
Lab #2 September 8, 2016 September 15, 2016
Lab #3 September 15, 2016 September 27, 2016
Lab #4 October 4, 2016 October 13, 2016
Project #1 October 13, 2016 November 3, 2016
Lab #5 November 8, 2016 November 29, 2016
Project #2 November 10, 2016 December 7, 2016

Useful Documents and Files

Document Description
ModelSim_GUI_Introduction.pdf Introduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor
Using_ModelSim.pdf Using ModelSim to Simulate Logic Circuits for Altera FPGA Devices
DE0_CV.qsf DE0_CV Quartus Settings File
DE0_CV.sdc DE0_CV Synopsys Design Constraints File
DE0_CV_Datasheets.zip DE0_CV Datasheets
DE0_CV_User_Manual.pdf DE0_CV User Manual
clk_div.vhd VHDL-based Clock Divider (50MHz input clock)