Digital Systems Design -- Lectures

Lecture Topic Files
Lecture 1 Digital Systems Design and Test PDF
Lecture 2 Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits PDF
Lecture 3 Review of VHDL for Sequential Circuits PDF
  VHDL Syntax Cheat Sheet PDF
Lecture 4 Guidelines for VHDL-based Design PDF
  ModelSim Simulation Example (Up Counter) ZIP
  ModelSim Simulation Example (Rotate Register) ZIP
Lecture 5 Programmable Device Technologies and Introduction to the Altera Cyclone V FPGA PDF
Lecture 6 Memory Implementation on Altera CYCLONE V Devices PDF
  Memory Creation Examples ZIP
  Exam #1 Sample Questions PDF
  Exam #1 Sample Questions (with solutions) PDF
Lecture 7 A Simple Computer Design PDF
  Simple Computer Example (with simulation) ZIP
Lecture 8 In-System Memory Content Editor and SignalTap II Logic Analyzer PDF
  Glitch-Free Clock Multiplexer Example (with simulation) ZIP
  Debounce Examples (with simulation) ZIP
  In-System Memory Content Editor Example ZIP
  SignalTap II Logic Analyzer Example ZIP
Lecture 9 Clock Networks and Phase Lock Loops on Altera Cyclone V Devices PDF
  PLL Example (with SignalTap II Logic Analyzer) ZIP
Lecture 10 Video Signal Generation for the Altera DE Board PDF
  Simple Video Example (built for DE0-CV board) ZIP
  Text Video Example (built for DE0-CV board) ZIP
  Text Video Example II, displaying a register value (built for DE0-CV board) ZIP
  Graphics Video Example (built for DE0-CV board) ZIP
Lecture 11 Introduction to System on a Programmable Chip PDF
  Exam #2 Sample Questions PDF
  Exam #2 Sample Questions (with solutions) PDF
  DE CPU (built for DE0-CV board) ZIP