| Lecture |
Topic |
PDF |
| Lecture 1 |
Digital Systems Design and Test |
PDF |
| Lecture 2 |
Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits |
PDF |
| Lecture 3 |
Review of VHDL for Sequential Circuits |
PDF |
| Lecture 4 |
Guidelines for VHDL-based Design |
PDF |
| Lecture 5 |
Programmable Device Technologies and Introduction to the Altera Cyclone II FPGA |
PDF |
| Lecture 6 |
Memory Implementation on Altera Cyclone II Devices |
PDF |
| Lecture 7 |
DE2 LCD Display Controller |
PDF |
| |
Exam #1 Sample Questions |
PDF |
| |
VHDL Cheat Sheet |
PDF |
| Lecture 8 |
In-System Memory Content Editor and SignalTap II Logic Analyzer |
PDF |
| Lecture 9 |
A Simple Computer Design |
PDF |
| Lecture 10 |
Global Clock Network and Phase Lock Loops on Altera Cyclone II Devices |
PDF |
| Lecture 11 |
Video Signal Generation for the Altera DE2 Board |
PDF |
| |
Bouncing "ball" Video Display VHDL Example |
VHDL |
| |
Text-based Video Display VHDL Example |
VHDL |
| Lecture 12 |
Introduction to System on a Programmable Chip |
PDF |
| Lecture 13 |
Altera NIOS II Software Development |
PDF |
| |
RPDS NIOS II Software Example (C code) |
C Source Code |
| |
RPDS NIOS II Software Example (C header file) |
C Header File |
| Lecture 14 |
SOPC Builder and NIOS II Hardware Development |
PDF |
| |
Lecture 14 Example Design |
ZIP file |
| Lecture 15 |
Custom Components for NIOS II Systems |
PDF |
| |
Exam #2 Sample Questions |
PDF |
| |
Lecture 15 Example Design |
ZIP file |
| |
Exam #2 Sample Questions (with solutions) |
PDF |
| |
Lecture 15 Example Design 2 |
ZIP file |